CV

Education

• M.S. in Integrated Circuit Engineering, Southeast University (SEU), 2026 - Present
  • Electronic Design Automation (EDA) Lab
  • Supervisor: Prof. Yarui Peng
• B.S. in Integrated Circuit Design and Integrated Systems, Nanjing University of Posts and Telecommunications (NJUPT), 2022 - 2026
  • Thesis: Design of a P-band Broadband Power Amplifier Based on LDMOS

Skills

• Hardware Description Languages & FPGA: Verilog HDL, FPGA prototyping and debugging.
• EDA & Simulation Tools: Cadence, Advanced Design System (ADS), Vivado, ModelSim.
• Programming & Software: C++, Python, Linux environment, Data Structures and Algorithms.

Experience & Projects

All-Digital Phase-Locked Loop (ADPLL) Design

• Designed and implemented an All-Digital Phase-Locked Loop system.
• Utilized Verilog for RTL coding and performed functional simulation and verification using ModelSim.

Direct Digital Synthesizer (DDS) Signal Generator

• Developed a DDS-based digital signal generator on FPGA platform.
• Configured and synthesized the design using Vivado, optimizing logic resource utilization and ensuring accurate waveform generation.

M-Sequence Extraction Engine

• Implemented the logic design for Maximum Length Sequence (M-sequence) extraction.
• Conducted rigorous simulation and timing analysis to ensure reliable pseudo-random sequence generation for digital communication applications.

P-band Broadband Power Amplifier Design (Undergraduate Thesis)

• Completed the systematic design and simulation of a P-band broadband power amplifier utilizing LDMOS technology.
• Conducted extensive layout design, boundary pin placement, and performance tuning using industry-standard RF simulation tools.

Integrated Circuit Innovation and Entrepreneurship Competition

• Participated in hardware design and structural problem-solving, utilizing 3D modeling and printing technologies to overcome mechanical limitations in robotic arm integration.